The present invention relates to a semiconductor integrated circuit for receiving a specified signal such as a carrier signal and a feedback signal outputted from a voltage control oscillator for outputting a synchronous signal based on the specified signal, comparing the phase of the specified signal to the phase of the feedback signal and outputting a comparison signal indicating a result of comparison to the voltage control oscillator, and more specifically to a semiconductor integrated circuit for forming a PLL (Phase-Locked Loop) to perform a locking operation.
FIG. 1 is a block diagram showing schematic configuration of a PLL circuit based on the conventional technology. In FIG. 1, the conventional type of PLL circuit comprises a phase comparator 102, a charge pump 103, a loop filter 104, a voltage control oscillator 105, and a 1/N divider 106.
Herein, especially a PLL circuit for receiving a carrier signal indicating an FM input signal as an input signal and obtaining a synchronous signal to this carrier signal is described. In FIG. 1, the phase comparator 102 compares a timing of the rising point of the received carrier signal to that of an oscillation signal received from the voltage control oscillator 105 through the 1/N divider 106 (an oscillation signal received from the voltage control oscillator 105 through the 1/N divider 106 is referred to as an internal oscillation signal hereinafter), and when an rising of the internal oscillation signal is delayed as compared to the carrier signal, namely when the frequency of the internal oscillation signal is lower than the frequency of the carrier signal inputs a signal UP as a low level into the gate of a P channel type of MOS transistor 112 in the charge pump 103 during that period.
On the other hand, when the rising of the internal oscillation signal is leading the carrier signal, namely when a frequency of the internal oscillation signal is higher than the frequency of the carrier signal inputs a signal DOWN as a high level into the gate of a N channel type of MOS transistor 113 in the charge pump 103 during that period.
The charge pump 103 is configured so that a current source 111, the P channel type of MOS transistor 112, the N channel type of MOS transistor 113, and a current source 114 are serially connected to each other between a power unit and the ground, and a node (node N) of the MOS transistor 112 and MOS transistor 113 is connected to the voltage control oscillator 105 through the loop filter 104.
When a signal UP indicating a low level is inputted into the gate of the MOS transistor 112 the MOS transistor 112 is turned ON and a positive charge is supplied from the current source 111 to the node N. Namely, a positive charge is supplied to the loop filter 104 that is provided in the next stage. The amplitude of this positive charge is obtained by integrating the current values for the current source 111 over a period of time for which the signal UP keeps on indicating the low level.
On the other hand, when a signal DOWN indicating a high level is inputted into the gate of the MOS transistor 113, the MOS transistor 113 is turned on and a negative charge is supplied from the current source 114 to the node N. Namely, a negative charge is supplied to the loop filter 104 provided in the next stage. The amplitude of this negative charge is obtained by integrating the current values for the current source 114 over a period of time for which the signal DOWN keeps on indicating the high level.
The loop filter 104 is configured so that a resistor 115 and a capacitor 116 are serially connected to each other between a node N and the ground and it accumulates the charge supplied from the charge pump 103 in the capacitor 116 through the resistor 115 and generates a control voltage for controlling the voltage control oscillator 105 provided in the next stage.
The voltage control oscillator 105 is an oscillator for outputting a signal with a frequency decided according to a control voltage, and can obtain this oscillation signal as a synchronous signal. Further, this oscillation signal is inputted into the 1/N divider 106. The 1/N divider 106 subjects the oscillation signal from the voltage control oscillator 105 to 1/N-division so that the frequency of the oscillation signal from the voltage control oscillator 105 coincides with the frequency of the carrier signal, and outputs the subjected signal as an internal oscillation signal as described above. This internal oscillation signal is inputted again into the phase comparator 102, which effects formation of a negative feedback loop for receiving an output signal as an input signal again.
Thus, the PLL circuit increases the frequency of the internal oscillation signal by feeding a positive voltage corresponding to the phase difference to the voltage control oscillator 105 as a control signal when the phase of the internal oscillation signal is delayed with respect to the carrier signal. Namely, a higher frequency can make the phase lead. When the phase of the internal oscillation signal leads the carrier signal the frequency of the internal oscillation signal is lowered by feeding a negative voltage corresponding to the phase difference to the voltage control oscillator 105 as a control signal. Namely, a lower frequency can make the phase delayed.
By the action of negative feedback described above, the frequency of the internal oscillation signal coincides with the carrier signal in its frequency as well as phase thereof, therefore, a synchronous signal that accurately indicates the frequency of the carrier signal can be outputted. The state where the frequency of this carrier signal coincides with that of the internal oscillation signal is termed as a locked state, and the period of time required to reach this locked state is termed as lock-up time.
In the PLL circuit shown in FIG. 1, operations of the charge pump 103 as well as the loop filter 104 can equivalently be realized by a digital circuit and there has been distributed a digital PLL obtained by changing the configuration including those components described above, phase comparator 102, voltage control oscillator 105, and 1/N divider 106 to a digital format.
The digital PLL, especially a PLL-IC obtained by forming the digital PLL to an IC is applied in a digital system such as an FSK modem demodulator for demodulating an A/D converted carrier signal and a frequency synthesizer for a transceiver.
However, in the conventional type of PLL circuit, a locked stage is unlocked when a carrier signal is not inputted because of its being shut off due to an external factor or the like or when a carrier signal outside an effective range of a frequency is inputted, and when an appropriate carrier signal is again inputted a sequential operation for reaching the locked state again (described a locking operation hereinafter) is required to be performed. As described above, a long time is required for the lock-up operation, therefore, a synchronous signal can not speedily be obtained.
The present invention was made to solve the problems described above, and it is an object of the present invention to perform a high-speed locking operation and realize a high-speed and stable feedback loop operation when an appropriate carrier signal is inputted again after entry of a carrier signal is cut off or a carrier signal outside an effective range of a frequency is inputted.
In order to solve the above problems and achieve the object, in the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal (such as a carrier signal) to that of an internal oscillation signal (a feedback signal) outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a carrier signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the specified signal or the comparison signal outputted from the phase comparing unit to a signal for maintaining the internal oscillation signal having been outputted up to the time just before switching from the voltage control oscillator according to the oscillating state detected by the oscillating state detector, namely to a control signal inputted into the voltage control oscillator to make the oscillator keep on outputting the internal oscillation signal.
With the above invention, an oscillating state of the specified signal is detected by the carrier detector, and the specified signal or the comparison signal is switched to a signal for maintaining oscillation and output of an internal oscillation signal outputted from the voltage control oscillator according to the detected oscillating state, so that, for example, when the specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the internal oscillation signal is not cut off by inputting a signal For making the voltage control oscillator keep on outputting an internal oscillation signal having been outputted up to the time just before switching from the voltage control oscillator therein, therefore, when a normal specified signal is inputted again, a locking operation can be speeded up as compared to the case where a feedback loop operation is started from the state in which the internal oscillation signal is not outputted from the voltage control oscillator, namely from the state in which there is no feedback signal.
According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching entry to the phase comparing unit from the specified signal to a previously-prepared signal (clock 2) with a specified frequency according to the oscillating state detected by the oscillating state detector.
With the above invention, an oscillating state of the specified signal is detected by the oscillating state detector, and the specified signal is switched to the clock 2 to be inputted into the phase comparing unit according to the detected oscillating state, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, therefore, a lock-up time required when an effective signal is detected again can be reduced, which allows a high-speed and stable feedback loop operation to be realized.
According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the comparison signal outputted from the phase comparing unit to a signal generated depending on a constant voltage source or a constant current source according to the oscillating state detected by the oscillating state detector.
With the above invention, an oscillating state of the specified signal is detected and the comparison signal is switched to a signal generated depending on the constant voltage source for supplying a specified voltage or the constant current source for supplying a specified charge according to the detected oscillating state, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, therefore, a lock-up time required when an effective signal is detected again can be reduced, which allows a high-speed and stable feedback loop operation to be realized.
According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises a holding unit for holding therein the comparison signal outputted from the phase comparing unit; an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the comparison signal to a voltage held in the holding unit according to the oscillating state detected by the oscillating state detector.
With the above invention, the comparison signal outputted from the phase comparing unit is held in the holding unit, and the signal switch switches entry to a loop filter or the voltage control oscillator from the comparison signal to a voltage held in the holding unit according to the oscillating state of the specified signal detected by the oscillating state detector, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, and a feedback signal according to the comparison signal in the previous locked state is inputted, therefore, a lock-up time required when an effective signal is detected again can further be reduced, which allows a high-speed and stable feedback loop operation to be realized.
According to one feature of the present invention, a semiconductor integrated circuit in addition has a oscillating state detector which checks presence of the specified signal and/or a frequency of the specified signal, and outputs, when it is determined that the specified signal is not being inputted or that a frequency of the specified signal is outside a prespecified range, a detection signal indicating that an oscillating state of the specified signal does not satisfy prespecified requirements; and a signal switch which switches the specified signal or the comparison signal outputted from the phase comparing unit to a signal for maintaining an internal oscillation signal according to this detection signal.
According to one feature of the present invention, a semiconductor integrated circuit in addition has a oscillating state detector comprising a counter for counting a pulse number of the specified signal during a specified period of time according to an external clock (clock 1) or a number of external clocks during a specified period of time according to the specified signal, and a condition comparing unit for comparing a pulse number or a pulse number of the clock 1 counted by the counter to a comparison object value indicating the prespecified range for a frequency of the specified signal and outputting a condition comparison signal, and also the specified detector outputs the detection signal according to the condition comparison signal.
According to one feature of the present invention, a semiconductor integrated circuit in addition has a voltage control oscillator internally provided therein as one of the components to form a PLL (Phase-Locked Loop).
With the above invention, the voltage control oscillator is internally provided therein, and a function as the PLL circuit for controlling the voltage control oscillator is effected by a control voltage generated according to the comparison signal outputted from the phase comparing unit, so that an external circuit for functioning as the PLL circuit is reduced, which allows an operation of the PLL by one chip and minimization of the PLL circuit to be achieved.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.